Post-Etch Inspection in Semiconductor Manufacturing: Methods and Tools
Averroes
Oct 28, 2026
Post-etch inspection, also called after-etch inspection (AEI), is the inline defect inspection of a wafer immediately after etch and resist strip, checking that the pattern transferred into the layer is complete and free of etch defects such as residue, under-etch, over-etch, profile distortion and opens or shorts. It runs inside every patterning cycle, alongside, but distinct from, the post-etch metrology that measures dimensions and overlay.
AEI is a per-cycle gate inside Stage 03 of the 12-stage semiconductor manufacturing process, repeated at every patterned layer. This guide from Averroes.ai, an AI visual inspection platform for manufacturers, maps each etch defect to its mechanism, the tool that catches it and the control loop its data feeds.
Key Notes
Etch is the most repeated front-end step, so AEI runs dozens of times per wafer, once per patterned layer.
Each etch failure mode has its own signature: residue where material should be gone, missing pattern where it should remain, distorted sidewalls in between.
Unlike the resist gates, an etch defect is already in the layer. AEI exists for containment and per-cycle feedback, not rework.
Optical tools find the defects; e-beam voltage contrast finds the invisible ones, opens and shorts buried in the structure.
What Is Post-Etch Inspection, and What Is It Not?
Post-etch inspection is inline defect inspection of the etched layer: it answers whether the pattern transferred completely and cleanly, not how precisely its dimensions landed. The distinction matters because two different tool families run after etch and get blended together. Defect inspection scans wafers for residue, pattern errors and structural flaws. Post-etch metrology, CD-SEM, overlay tools and scatterometry, measures how wide, how aligned and how tall the features are. This page covers the first; the measurement side has its own guides.
One more boundary is worth a sentence. Endpoint detection, usually optical emission spectroscopy, tells the etcher when the layer has cleared so the process can stop. It is control inside the etch chamber, not inspection of the wafer that leaves it.
Etch defects at a glance
Defect
Mechanism
Looks Like on the Tool
Caught By
Residue and polymer
Byproducts not fully removed
Blocked spaces, sidewall film
Optical, review
Under-etch
Etch stopped early
Bridges between features
Optical die-to-die
Over-etch
Etch ran long or deep
Broken or thinned lines
Optical die-to-die
Profile defects
Anisotropy lost
Undercut, bowed sidewalls
Cross-section, metrology
Opens and shorts
Discontinuity in the circuit
Often invisible optically
E-beam voltage contrast
Plasma damage
Charge during etch
No visible mark
Electrical test, sampling
Corrosion
Chlorine residue plus moisture
Spreading stains on metal
Optical, timed inspection
Where AEI Sits in the Patterning Cycle
Each patterned layer runs lithography, etch, strip and clean, then post-etch inspection, before the next film goes down. A leading-edge device repeats that cycle dozens of times, so the gate’s economics compound: a defect caught at this cycle is contained to one layer, while the same defect found at end of line has every layer above it built on top.
AEI is the third gate in the cycle’s chain. Photoresist inspection qualifies the coated film, post-develop inspection qualifies the printed pattern while rework is still possible, and AEI verifies what the etch actually did to the layer the photolithography process patterned. Rework ends where etch begins: the resist gates protect the etch, and AEI measures the result.
The loop makes the page’s central point: AEI is not one checkpoint but a gate the wafer passes dozens of times, which is what makes its data a process signal.
What Defects Does Etch Create?
Etch defects are the residues, pattern errors and structural flaws created while material is removed, distinct from the resist defects caught at the gates before etch. Each family has its own mechanism, and the mechanism is what classified inspection data points back at.
The gallery carries the section’s takeaway: residue is material that stayed, pattern defects are material that went missing, and the worst defects are the ones optics cannot see at all.
Residue and Polymer
Etch residue is process byproduct left on the structure after etch and strip: redeposited material in the spaces, or the sidewall polymer that anisotropic etching deliberately forms and the strip must then remove completely. Leftover residue blocks contacts, narrows spaces and, on metal layers, seeds corrosion. Post-etch cleaning chemistry exists to remove it; inspection exists to confirm the cleaning worked.
Under-Etch
Under-etch is material left where it should be gone, because the etch stopped early or slowed locally. Its signature is bridging: thin connections between features that should be separate, which become electrical shorts once the layer is wired. On a die-to-die comparison it reads as extra material repeated at the weak point of the pattern.
Over-Etch
Over-etch is the opposite loss: the etch ran long or attacked laterally, thinning the protected pattern or biting into the layer below. Broken lines, thinned etch stops and punched-through contacts are its signatures. Some deliberate over-etch is part of every recipe; the defect is the excursion beyond it.
Profile Defects
Profile defects are distortions of the sidewall shape: undercut beneath the mask, bowed sidewalls, unintended taper, or micro-trenching where the etch digs grooves at the feature’s base. Plasma etching is used precisely because it is anisotropic, removing material vertically, and a lost profile gives it up. The consequence lands one step later: the next deposition has to fill or cover the distorted shape, and voids or thin spots follow.
The cross-sections restate the point in one glance: the pattern can be present and still be wrong in shape.
Opens and Shorts
Opens and shorts are electrical discontinuities: a conductor that should connect and does not, or two that should not and do. Many are invisible to optics, buried at the bottom of a contact or inside a dense structure, which is why they get their own inspection method below. They are the defects with the least warning and the highest cost.
Plasma Damage and Corrosion
Plasma damage is charge-induced harm to sensitive structures, gate oxides above all, accumulated while the wafer sits in the plasma. It leaves no visible mark and surfaces as electrical failure, which keeps it a sampling and test concern rather than an imaging one. Post-etch corrosion is its visible cousin on metal layers: chlorine-bearing residues meet ambient moisture and attack the metal, which is why metal-etch wafers are cleaned and inspected on a clock.
How Are Etch Defects Detected? Methods and Tools
AEI combines fast optical inspection of every wafer with e-beam inspection where electrical defects hide, and sends what gets flagged to review.
Patterned-Wafer Optical Inspection
Optical inspection is the workhorse: it images the patterned wafer and compares die against die, flagging anything that breaks the repetition. Bright field inspection resolves pattern anomalies, residue and missing features in reflected light; dark field inspection catches particles and small scatterers that bright field washes out. Because every die should match its neighbors, the comparison itself is the detector, and it runs fast enough to inspect inline at every cycle.
E-Beam and Voltage Contrast Inspection
E-beam inspection scans the wafer with an electron beam and reads the charge each structure holds. A floating structure that should be grounded, or a grounded one that should float, charges differently and shows as contrast: an open or a short made visible without touching the circuit. The trade is throughput. E-beam is slow, so it runs on sampled wafers and the layers where buried electrical defects concentrate, while optical inspection covers everything else.
Review and Classification
Flagged sites go to review imaging for a closer look, and classification turns the anomaly list into named defect classes. That naming is what makes the rest of this page’s argument possible: a count of “defects” trends nothing, while a count of residue, bridges or corrosion points at a cause.
From Inspection to Control: The Per-Cycle Feedback Loop
Because etch repeats at every layer, classified AEI data is a per-cycle process signal: trended by layer, chamber and recipe, it turns defect counts into excursion detection. A residue signature rising on one chamber is a clean or a part change. A profile drift confined to one recipe is a process adjustment. A bridge count climbing on one layer flags the litho-etch interaction behind it. Caught this cycle, the correction protects every lot behind the one that showed it; the same signal discovered at end of line arrives months of processing too late. Chamber matching runs on the same data: identical recipes on identical chambers should produce identical defect signatures, and classified trends are what show when they stop doing so.
The schematic shows the destination of everything above it: an inspection gate becomes a control loop the moment its output is classified and trended.
Averroes.ai runs as an overlay on the optical, e-beam and review tools already installed at the etch gate. It trains classification models from 20 to 40 labeled images per defect class, with no code, and deploys on premise so wafer image data stays inside the fab. AI defect classification names the defect classes, and defect monitoring trends them by lot, layer, chamber and recipe, which is the per-cycle feedback this page describes. It augments the installed inspection tools; it does not replace them.
Is AEI Feeding Back Fast Enough?
See defect monitoring on your own post-etch inspection images
Frequently Asked Questions
What is after-etch inspection (AEI)?
After-etch inspection is the inline defect inspection that runs immediately after etch and resist strip, confirming the pattern transferred into the layer completely and cleanly. It looks for etch residue, bridging, broken lines, profile distortion and electrical opens or shorts, and it repeats at every patterned layer of the device.
What defects does etching cause?
Etching can leave residue and sidewall polymer, bridge features through under-etch, break or thin them through over-etch, distort sidewall profiles through undercut, bowing or micro-trenching, create electrical opens and shorts, damage charge-sensitive structures in the plasma, and seed corrosion on metal layers when chlorine residues meet moisture.
What is etch residue?
Etch residue is process byproduct left on the wafer after etch and strip: redeposited material in the etched spaces or sidewall polymer the strip did not fully remove. It blocks contacts, narrows spaces and can seed corrosion on metal. Post-etch cleaning removes it, and inspection confirms the cleaning worked.
What is the difference between under-etching and over-etching?
Under-etching leaves material where it should be gone, typically bridging neighboring features into electrical shorts. Over-etching removes material it should have spared, breaking or thinning lines and biting into the layer below. One is an etch that stopped too early; the other ran too long or too wide.
What is the difference between post-develop and post-etch inspection?
Post-develop inspection checks the printed resist pattern before etch, while the wafer can still be stripped and reworked. Post-etch inspection checks the layer after etch has transferred the pattern permanently. The first gate exists to prevent a bad pattern from being etched; the second exists to contain and correct what the etch did.
What is the most common etching technique in semiconductor manufacturing?
Plasma-based dry etching, most commonly reactive ion etching (RIE), dominates pattern transfer because it removes material anisotropically and holds the vertical sidewalls dense features require. Wet chemical etching still serves cleans and non-critical removal, where selectivity matters more than directionality.
Post-etch inspection, also called after-etch inspection (AEI), is the inline defect inspection of a wafer immediately after etch and resist strip, checking that the pattern transferred into the layer is complete and free of etch defects such as residue, under-etch, over-etch, profile distortion and opens or shorts. It runs inside every patterning cycle, alongside, but distinct from, the post-etch metrology that measures dimensions and overlay.
AEI is a per-cycle gate inside Stage 03 of the 12-stage semiconductor manufacturing process, repeated at every patterned layer. This guide from Averroes.ai, an AI visual inspection platform for manufacturers, maps each etch defect to its mechanism, the tool that catches it and the control loop its data feeds.
Key Notes
What Is Post-Etch Inspection, and What Is It Not?
Post-etch inspection is inline defect inspection of the etched layer: it answers whether the pattern transferred completely and cleanly, not how precisely its dimensions landed. The distinction matters because two different tool families run after etch and get blended together. Defect inspection scans wafers for residue, pattern errors and structural flaws. Post-etch metrology, CD-SEM, overlay tools and scatterometry, measures how wide, how aligned and how tall the features are. This page covers the first; the measurement side has its own guides.
One more boundary is worth a sentence. Endpoint detection, usually optical emission spectroscopy, tells the etcher when the layer has cleared so the process can stop. It is control inside the etch chamber, not inspection of the wafer that leaves it.
Etch defects at a glance
Where AEI Sits in the Patterning Cycle
Each patterned layer runs lithography, etch, strip and clean, then post-etch inspection, before the next film goes down. A leading-edge device repeats that cycle dozens of times, so the gate’s economics compound: a defect caught at this cycle is contained to one layer, while the same defect found at end of line has every layer above it built on top.
AEI is the third gate in the cycle’s chain. Photoresist inspection qualifies the coated film, post-develop inspection qualifies the printed pattern while rework is still possible, and AEI verifies what the etch actually did to the layer the photolithography process patterned. Rework ends where etch begins: the resist gates protect the etch, and AEI measures the result.
The loop makes the page’s central point: AEI is not one checkpoint but a gate the wafer passes dozens of times, which is what makes its data a process signal.
What Defects Does Etch Create?
Etch defects are the residues, pattern errors and structural flaws created while material is removed, distinct from the resist defects caught at the gates before etch. Each family has its own mechanism, and the mechanism is what classified inspection data points back at.
The gallery carries the section’s takeaway: residue is material that stayed, pattern defects are material that went missing, and the worst defects are the ones optics cannot see at all.
Residue and Polymer
Etch residue is process byproduct left on the structure after etch and strip: redeposited material in the spaces, or the sidewall polymer that anisotropic etching deliberately forms and the strip must then remove completely. Leftover residue blocks contacts, narrows spaces and, on metal layers, seeds corrosion. Post-etch cleaning chemistry exists to remove it; inspection exists to confirm the cleaning worked.
Under-Etch
Under-etch is material left where it should be gone, because the etch stopped early or slowed locally. Its signature is bridging: thin connections between features that should be separate, which become electrical shorts once the layer is wired. On a die-to-die comparison it reads as extra material repeated at the weak point of the pattern.
Over-Etch
Over-etch is the opposite loss: the etch ran long or attacked laterally, thinning the protected pattern or biting into the layer below. Broken lines, thinned etch stops and punched-through contacts are its signatures. Some deliberate over-etch is part of every recipe; the defect is the excursion beyond it.
Profile Defects
Profile defects are distortions of the sidewall shape: undercut beneath the mask, bowed sidewalls, unintended taper, or micro-trenching where the etch digs grooves at the feature’s base. Plasma etching is used precisely because it is anisotropic, removing material vertically, and a lost profile gives it up. The consequence lands one step later: the next deposition has to fill or cover the distorted shape, and voids or thin spots follow.
The cross-sections restate the point in one glance: the pattern can be present and still be wrong in shape.
Opens and Shorts
Opens and shorts are electrical discontinuities: a conductor that should connect and does not, or two that should not and do. Many are invisible to optics, buried at the bottom of a contact or inside a dense structure, which is why they get their own inspection method below. They are the defects with the least warning and the highest cost.
Plasma Damage and Corrosion
Plasma damage is charge-induced harm to sensitive structures, gate oxides above all, accumulated while the wafer sits in the plasma. It leaves no visible mark and surfaces as electrical failure, which keeps it a sampling and test concern rather than an imaging one. Post-etch corrosion is its visible cousin on metal layers: chlorine-bearing residues meet ambient moisture and attack the metal, which is why metal-etch wafers are cleaned and inspected on a clock.
How Are Etch Defects Detected? Methods and Tools
AEI combines fast optical inspection of every wafer with e-beam inspection where electrical defects hide, and sends what gets flagged to review.
Patterned-Wafer Optical Inspection
Optical inspection is the workhorse: it images the patterned wafer and compares die against die, flagging anything that breaks the repetition. Bright field inspection resolves pattern anomalies, residue and missing features in reflected light; dark field inspection catches particles and small scatterers that bright field washes out. Because every die should match its neighbors, the comparison itself is the detector, and it runs fast enough to inspect inline at every cycle.
E-Beam and Voltage Contrast Inspection
E-beam inspection scans the wafer with an electron beam and reads the charge each structure holds. A floating structure that should be grounded, or a grounded one that should float, charges differently and shows as contrast: an open or a short made visible without touching the circuit. The trade is throughput. E-beam is slow, so it runs on sampled wafers and the layers where buried electrical defects concentrate, while optical inspection covers everything else.
Review and Classification
Flagged sites go to review imaging for a closer look, and classification turns the anomaly list into named defect classes. That naming is what makes the rest of this page’s argument possible: a count of “defects” trends nothing, while a count of residue, bridges or corrosion points at a cause.
From Inspection to Control: The Per-Cycle Feedback Loop
Because etch repeats at every layer, classified AEI data is a per-cycle process signal: trended by layer, chamber and recipe, it turns defect counts into excursion detection. A residue signature rising on one chamber is a clean or a part change. A profile drift confined to one recipe is a process adjustment. A bridge count climbing on one layer flags the litho-etch interaction behind it. Caught this cycle, the correction protects every lot behind the one that showed it; the same signal discovered at end of line arrives months of processing too late. Chamber matching runs on the same data: identical recipes on identical chambers should produce identical defect signatures, and classified trends are what show when they stop doing so.
The schematic shows the destination of everything above it: an inspection gate becomes a control loop the moment its output is classified and trended.
Averroes.ai runs as an overlay on the optical, e-beam and review tools already installed at the etch gate. It trains classification models from 20 to 40 labeled images per defect class, with no code, and deploys on premise so wafer image data stays inside the fab. AI defect classification names the defect classes, and defect monitoring trends them by lot, layer, chamber and recipe, which is the per-cycle feedback this page describes. It augments the installed inspection tools; it does not replace them.
Is AEI Feeding Back Fast Enough?
See defect monitoring on your own post-etch inspection images
Frequently Asked Questions
What is after-etch inspection (AEI)?
After-etch inspection is the inline defect inspection that runs immediately after etch and resist strip, confirming the pattern transferred into the layer completely and cleanly. It looks for etch residue, bridging, broken lines, profile distortion and electrical opens or shorts, and it repeats at every patterned layer of the device.
What defects does etching cause?
Etching can leave residue and sidewall polymer, bridge features through under-etch, break or thin them through over-etch, distort sidewall profiles through undercut, bowing or micro-trenching, create electrical opens and shorts, damage charge-sensitive structures in the plasma, and seed corrosion on metal layers when chlorine residues meet moisture.
What is etch residue?
Etch residue is process byproduct left on the wafer after etch and strip: redeposited material in the etched spaces or sidewall polymer the strip did not fully remove. It blocks contacts, narrows spaces and can seed corrosion on metal. Post-etch cleaning removes it, and inspection confirms the cleaning worked.
What is the difference between under-etching and over-etching?
Under-etching leaves material where it should be gone, typically bridging neighboring features into electrical shorts. Over-etching removes material it should have spared, breaking or thinning lines and biting into the layer below. One is an etch that stopped too early; the other ran too long or too wide.
What is the difference between post-develop and post-etch inspection?
Post-develop inspection checks the printed resist pattern before etch, while the wafer can still be stripped and reworked. Post-etch inspection checks the layer after etch has transferred the pattern permanently. The first gate exists to prevent a bad pattern from being etched; the second exists to contain and correct what the etch did.
What is the most common etching technique in semiconductor manufacturing?
Plasma-based dry etching, most commonly reactive ion etching (RIE), dominates pattern transfer because it removes material anisotropically and holds the vertical sidewalls dense features require. Wet chemical etching still serves cleans and non-critical removal, where selectivity matters more than directionality.