Post-CMP Inspection: Detecting Scratches, Dishing and Slurry Residue on Wafers
Averroes
Oct 29, 2026
Post-CMP inspection is the inline defect check that runs after chemical mechanical planarization (CMP) and the post-CMP clean, catching the micro-scratches, slurry residue, delamination and corrosion the polish and clean can leave on a wafer. It runs alongside, but distinct from, the metrology that measures dishing and erosion, and it verifies what the post-CMP clean was supposed to remove. The gate repeats with every CMP pass, dozens of times per wafer at advanced nodes.
Post-CMP inspection is a per-cycle gate inside Stage 03 of the 12-stage semiconductor manufacturing process. This guide from Averroes.ai, an AI visual inspection platform for manufacturers, maps each CMP defect to its mechanism, the tool that catches it and the measurement that decides what happens to the wafer.
Key Notes
At advanced nodes CMP runs dozens of times per wafer, and the post-CMP gate repeats with every pass.
Three different checks follow CMP: defects are inspected, dishing and erosion are measured, and cleanliness is verified after the post-CMP clean.
A micro-scratch on a planarized metal layer crosses every line in its path, so its length decides its cost.
Detection finds a scratch and classification names it. Segmentation measures it, and the measurement decides disposition.
What Is Post-CMP Inspection, and What Is It Not?
Post-CMP inspection is inline defect inspection of the planarized surface: it answers whether the polish and clean left scratches, residue or damage, not how flat the result is. The distinction matters because three different checks follow CMP and get blended together. Defect inspection scans the wafer for the flaws cataloged below. Topography metrology measures dishing, erosion and planarity on test structures with profilometry and optical metrology. And cleanliness is the post-CMP clean’s job: the clean removes slurry and byproducts, inspection verifies that it did, and surface metal contamination is measured separately by total reflection X-ray fluorescence (TXRF).
One bridge sentence covers the cleaning side: post-CMP cleaning, typically brush cleaning with megasonic assist, is required to remove particles, organic residues and metallic contaminants from the polished surface, and it is a process topic with its own literature. This page covers the gate that checks its result.
After CMP: what gets checked and how
Check
What It Looks For
Method
Covered Here
Defect inspection
Scratches, residue, delamination, corrosion
Darkfield, brightfield, review
Yes, in full
Topography
Dishing, erosion, planarity
Profilometry, optical metrology
Boundary section
Cleanliness
Particles, surface metals
Clean, then scan; TXRF
One sentence
Where the Post-CMP Gate Sits
Each CMP pass runs polish, post-CMP clean, then inspection, before the next film goes down. At advanced nodes that loop repeats dozens of times per wafer, so the gate’s economics compound the same way they do one gate upstream: the per-cycle feedback case is made at post-etch inspection, and it applies equally here, with pads, slurry and clean recipes as the consumables being watched.
One disambiguation keeps this page in its lane. CMP here is in-fab planarization, flattening each new metal or dielectric layer between build cycles. It is not the wafer polishing and surface preparation that finishes the bare substrate at the wafer supplier, though the chemistry is related. That page covers the substrate side; this one covers the gate the wafer passes dozens of times after it.
The loop is the page’s framing: this is not one checkpoint but a gate that repeats with every planarized layer, which is what makes its data worth trending.
What Defects Does CMP Create?
CMP defects are the mechanical and chemical flaws the polish and clean leave on the planarized surface, distinct from the topography errors measured by metrology. Each family has its own mechanism, and each points back at a consumable or a step.
The gallery carries the section’s takeaway: every post-CMP defect family has a signature, and the signature names the consumable or step that created it.
Micro-Scratches and Chatter Marks
Micro-scratches are linear mechanical damage cut into the planarized surface by oversized abrasive particles, agglomerated slurry or debris shed from the pad. They read as arcs and chatter trails that follow the polish motion. On a metal layer their cost scales with length: a scratch crossing a dense array can open or short every line in its path, which is why a micro scratch on a wafer is measured and not just counted. Pad age matters here, since worn pads shed more debris and scratch more.
Slurry Residue and Particles
Slurry residue is abrasive and polish byproduct still bonded to the surface after the post-CMP clean. It narrows spaces, blocks contact to the layer below and seeds defects in the next deposition, which has to grow over it. Residue that survives the clean is the gate’s most direct verdict on the clean itself.
Delamination and Peeling
Delamination is film pulled up from a weak interface under the shear of polishing, worst on mechanically fragile low-k dielectrics. It appears as lifted or missing film regions rather than point defects, and its cost is area-scale: everything patterned on the lifted region is lost.
Post-CMP Corrosion
Post-CMP corrosion is chemical and galvanic attack on freshly polished copper, driven by residual chemistry and moisture. It reads as spreading stains and recessed metal, and it keeps growing until the wafer is cleaned and passivated, which is why copper layers are cleaned and inspected on a clock rather than a queue.
Watermarks
Watermarks are drying marks left by the clean itself, where rinse water evaporated instead of being displaced. They are the reminder that the clean can create the defect it exists to prevent, and a watermark signature rising on one clean recipe points straight at that recipe.
Dishing and Erosion: Measured, Not Inspected
Dishing is the recess polished into a single wide metal feature; erosion is the thinning of a dense array of lines and the dielectric between them. Both come from the physics of the process: soft metal polishes faster than hard dielectric, and removal rate follows pattern density, so wide copper dishes and dense arrays erode. They are controlled by recipe, pad and slurry design, not eliminated.
Their cost arrives in two currencies. Electrically, a dished or eroded line is a thinner line, so resistance varies with layout. Optically, the recess is non-planarity that the next lithography step has to focus across, and because planarization errors stack, a few nanometers per layer compounds over dozens of layers.
They live on the metrology side of the split because a defect scanner does not measure depth. Dishing and erosion are measured on test structures with profilometry and optical metrology, as height values against a planarity budget. This page notes the boundary and leaves the measurement depth to metrology coverage.
The cross-section makes the distinction visible: dishing is one wide feature recessed, erosion is a whole neighborhood thinned.
How Are Post-CMP Defects Detected?
Post-CMP inspection leans on darkfield scanning, because a planarized surface is the best background a scatterer can have.
Darkfield as the Workhorse
Dark field inspection collects only scattered light, and a freshly planarized, mirror-like surface scatters almost nothing. Anything that does scatter, a scratch edge, a residue particle, a lifted film edge, stands out against a dark background. That is why darkfield runs both as blanket monitoring on unpatterned test wafers and as the fast full-wafer scan on product at the CMP gate.
Brightfield and Pattern Comparison
Bright field inspection images the patterned surface in reflected light and compares die against die, which is how area-scale and contrast defects get caught: delamination regions, corrosion stains and pattern damage that darkfield’s point-scatter logic underweights. Between the two modes, the gate covers both point defects and area defects at production speed.
Review and Disposition
Flagged sites go to review imaging to confirm what each detection is. Confirmation answers the first question, identity, and immediately raises the second: how big. That question belongs to the next section, because at this gate size is the decision. Deeper coverage of the tool landscape across all fab gates lives in the wafer inspection guide; this page stays on the CMP gate.
Why Segmentation Decides Disposition at the CMP Gate
Defect segmentation measures each detection at the pixel level: a scratch’s length and path, a residue patch’s area, a delamination’s extent. The CMP gate needs that measurement because its dispositions are quantitative. A short scratch in open dielectric and a scratch of the same class crossing a dense metal array are different decisions. A small residue patch and a large one on the same wafer are the difference between a reclean and a hold. Detection finds the defect and classification names it, but neither says how much of the wafer it touches, and that is the number disposition runs on.
Segmented metrics also sharpen the gate’s feedback role. Scratch length distributions trended against pad age, residue area trended against slurry batch and clean recipe, turn a recurring signature into a consumable change or a recipe adjustment, the same per-cycle logic the post-etch gate runs on classified counts.
Averroes.ai runs as an overlay on the darkfield, brightfield and review tools already installed at the CMP gate. Defect segmentation produces pixel-level masks for each defect, with AI defect detection running on the same images, trained from 20 to 40 labeled images per defect class, with no code, deployed on premise so wafer image data stays inside the fab. It augments the installed inspection tools; it does not replace them.
The overlay shows the argument in one frame: the mask is the measurement, and the measurement is the disposition input.
How Long Is That Scratch, Really?
See defect segmentation on your own post-CMP inspection images
Frequently Asked Questions
What is post-CMP inspection?
Post-CMP inspection is the inline defect check that runs after chemical mechanical planarization and the post-CMP clean. It looks for micro-scratches, slurry residue, delamination, corrosion and watermarks on the planarized surface, and it repeats with every CMP pass, dozens of times per wafer at advanced nodes.
What defects does CMP cause?
CMP can scratch the surface through oversized abrasives or pad debris, leave slurry residue the clean missed, pull up film as delamination at weak interfaces, seed corrosion on freshly polished copper, and leave watermarks from drying. It also produces dishing and erosion, which are topography errors measured by metrology rather than caught by defect inspection.
What causes scratches in CMP?
CMP scratches come from oversized or agglomerated abrasive particles in the slurry, debris shed by an aging polish pad, and hard contaminants trapped between pad and wafer. They cut arcs and chatter trails along the polish motion. Slurry filtration, pad conditioning and pad replacement are the usual countermeasures when a scratch signature rises.
What is the difference between dishing and erosion?
Dishing is the recess polished into a single wide metal feature because soft metal removes faster than the dielectric beside it. Erosion is the thinning of a dense array of lines together with the dielectric between them, driven by pattern density. Both are height errors, so they are measured by metrology rather than found by defect scanners.
What is slurry residue?
Slurry residue is abrasive particles and polish byproduct still bonded to the wafer after the post-CMP clean. It blocks contact to the layer below, narrows spaces and seeds defects in the next deposition. Persistent residue is a verdict on the clean, and its signature points at the slurry batch or clean recipe behind it.
Is post-CMP cleaning the same as post-CMP inspection?
No. Post-CMP cleaning is the process step that removes slurry, particles and chemical residue from the polished surface, usually by brush cleaning with megasonic assist. Post-CMP inspection is the check that follows it, scanning the wafer to verify the clean worked and the polish left no scratches, delamination or corrosion behind.
Post-CMP inspection is the inline defect check that runs after chemical mechanical planarization (CMP) and the post-CMP clean, catching the micro-scratches, slurry residue, delamination and corrosion the polish and clean can leave on a wafer. It runs alongside, but distinct from, the metrology that measures dishing and erosion, and it verifies what the post-CMP clean was supposed to remove. The gate repeats with every CMP pass, dozens of times per wafer at advanced nodes.
Post-CMP inspection is a per-cycle gate inside Stage 03 of the 12-stage semiconductor manufacturing process. This guide from Averroes.ai, an AI visual inspection platform for manufacturers, maps each CMP defect to its mechanism, the tool that catches it and the measurement that decides what happens to the wafer.
Key Notes
What Is Post-CMP Inspection, and What Is It Not?
Post-CMP inspection is inline defect inspection of the planarized surface: it answers whether the polish and clean left scratches, residue or damage, not how flat the result is. The distinction matters because three different checks follow CMP and get blended together. Defect inspection scans the wafer for the flaws cataloged below. Topography metrology measures dishing, erosion and planarity on test structures with profilometry and optical metrology. And cleanliness is the post-CMP clean’s job: the clean removes slurry and byproducts, inspection verifies that it did, and surface metal contamination is measured separately by total reflection X-ray fluorescence (TXRF).
One bridge sentence covers the cleaning side: post-CMP cleaning, typically brush cleaning with megasonic assist, is required to remove particles, organic residues and metallic contaminants from the polished surface, and it is a process topic with its own literature. This page covers the gate that checks its result.
After CMP: what gets checked and how
Where the Post-CMP Gate Sits
Each CMP pass runs polish, post-CMP clean, then inspection, before the next film goes down. At advanced nodes that loop repeats dozens of times per wafer, so the gate’s economics compound the same way they do one gate upstream: the per-cycle feedback case is made at post-etch inspection, and it applies equally here, with pads, slurry and clean recipes as the consumables being watched.
One disambiguation keeps this page in its lane. CMP here is in-fab planarization, flattening each new metal or dielectric layer between build cycles. It is not the wafer polishing and surface preparation that finishes the bare substrate at the wafer supplier, though the chemistry is related. That page covers the substrate side; this one covers the gate the wafer passes dozens of times after it.
The loop is the page’s framing: this is not one checkpoint but a gate that repeats with every planarized layer, which is what makes its data worth trending.
What Defects Does CMP Create?
CMP defects are the mechanical and chemical flaws the polish and clean leave on the planarized surface, distinct from the topography errors measured by metrology. Each family has its own mechanism, and each points back at a consumable or a step.
The gallery carries the section’s takeaway: every post-CMP defect family has a signature, and the signature names the consumable or step that created it.
Micro-Scratches and Chatter Marks
Micro-scratches are linear mechanical damage cut into the planarized surface by oversized abrasive particles, agglomerated slurry or debris shed from the pad. They read as arcs and chatter trails that follow the polish motion. On a metal layer their cost scales with length: a scratch crossing a dense array can open or short every line in its path, which is why a micro scratch on a wafer is measured and not just counted. Pad age matters here, since worn pads shed more debris and scratch more.
Slurry Residue and Particles
Slurry residue is abrasive and polish byproduct still bonded to the surface after the post-CMP clean. It narrows spaces, blocks contact to the layer below and seeds defects in the next deposition, which has to grow over it. Residue that survives the clean is the gate’s most direct verdict on the clean itself.
Delamination and Peeling
Delamination is film pulled up from a weak interface under the shear of polishing, worst on mechanically fragile low-k dielectrics. It appears as lifted or missing film regions rather than point defects, and its cost is area-scale: everything patterned on the lifted region is lost.
Post-CMP Corrosion
Post-CMP corrosion is chemical and galvanic attack on freshly polished copper, driven by residual chemistry and moisture. It reads as spreading stains and recessed metal, and it keeps growing until the wafer is cleaned and passivated, which is why copper layers are cleaned and inspected on a clock rather than a queue.
Watermarks
Watermarks are drying marks left by the clean itself, where rinse water evaporated instead of being displaced. They are the reminder that the clean can create the defect it exists to prevent, and a watermark signature rising on one clean recipe points straight at that recipe.
Dishing and Erosion: Measured, Not Inspected
Dishing is the recess polished into a single wide metal feature; erosion is the thinning of a dense array of lines and the dielectric between them. Both come from the physics of the process: soft metal polishes faster than hard dielectric, and removal rate follows pattern density, so wide copper dishes and dense arrays erode. They are controlled by recipe, pad and slurry design, not eliminated.
Their cost arrives in two currencies. Electrically, a dished or eroded line is a thinner line, so resistance varies with layout. Optically, the recess is non-planarity that the next lithography step has to focus across, and because planarization errors stack, a few nanometers per layer compounds over dozens of layers.
They live on the metrology side of the split because a defect scanner does not measure depth. Dishing and erosion are measured on test structures with profilometry and optical metrology, as height values against a planarity budget. This page notes the boundary and leaves the measurement depth to metrology coverage.
The cross-section makes the distinction visible: dishing is one wide feature recessed, erosion is a whole neighborhood thinned.
How Are Post-CMP Defects Detected?
Post-CMP inspection leans on darkfield scanning, because a planarized surface is the best background a scatterer can have.
Darkfield as the Workhorse
Dark field inspection collects only scattered light, and a freshly planarized, mirror-like surface scatters almost nothing. Anything that does scatter, a scratch edge, a residue particle, a lifted film edge, stands out against a dark background. That is why darkfield runs both as blanket monitoring on unpatterned test wafers and as the fast full-wafer scan on product at the CMP gate.
Brightfield and Pattern Comparison
Bright field inspection images the patterned surface in reflected light and compares die against die, which is how area-scale and contrast defects get caught: delamination regions, corrosion stains and pattern damage that darkfield’s point-scatter logic underweights. Between the two modes, the gate covers both point defects and area defects at production speed.
Review and Disposition
Flagged sites go to review imaging to confirm what each detection is. Confirmation answers the first question, identity, and immediately raises the second: how big. That question belongs to the next section, because at this gate size is the decision. Deeper coverage of the tool landscape across all fab gates lives in the wafer inspection guide; this page stays on the CMP gate.
Why Segmentation Decides Disposition at the CMP Gate
Defect segmentation measures each detection at the pixel level: a scratch’s length and path, a residue patch’s area, a delamination’s extent. The CMP gate needs that measurement because its dispositions are quantitative. A short scratch in open dielectric and a scratch of the same class crossing a dense metal array are different decisions. A small residue patch and a large one on the same wafer are the difference between a reclean and a hold. Detection finds the defect and classification names it, but neither says how much of the wafer it touches, and that is the number disposition runs on.
Segmented metrics also sharpen the gate’s feedback role. Scratch length distributions trended against pad age, residue area trended against slurry batch and clean recipe, turn a recurring signature into a consumable change or a recipe adjustment, the same per-cycle logic the post-etch gate runs on classified counts.
Averroes.ai runs as an overlay on the darkfield, brightfield and review tools already installed at the CMP gate. Defect segmentation produces pixel-level masks for each defect, with AI defect detection running on the same images, trained from 20 to 40 labeled images per defect class, with no code, deployed on premise so wafer image data stays inside the fab. It augments the installed inspection tools; it does not replace them.
The overlay shows the argument in one frame: the mask is the measurement, and the measurement is the disposition input.
How Long Is That Scratch, Really?
See defect segmentation on your own post-CMP inspection images
Frequently Asked Questions
What is post-CMP inspection?
Post-CMP inspection is the inline defect check that runs after chemical mechanical planarization and the post-CMP clean. It looks for micro-scratches, slurry residue, delamination, corrosion and watermarks on the planarized surface, and it repeats with every CMP pass, dozens of times per wafer at advanced nodes.
What defects does CMP cause?
CMP can scratch the surface through oversized abrasives or pad debris, leave slurry residue the clean missed, pull up film as delamination at weak interfaces, seed corrosion on freshly polished copper, and leave watermarks from drying. It also produces dishing and erosion, which are topography errors measured by metrology rather than caught by defect inspection.
What causes scratches in CMP?
CMP scratches come from oversized or agglomerated abrasive particles in the slurry, debris shed by an aging polish pad, and hard contaminants trapped between pad and wafer. They cut arcs and chatter trails along the polish motion. Slurry filtration, pad conditioning and pad replacement are the usual countermeasures when a scratch signature rises.
What is the difference between dishing and erosion?
Dishing is the recess polished into a single wide metal feature because soft metal removes faster than the dielectric beside it. Erosion is the thinning of a dense array of lines together with the dielectric between them, driven by pattern density. Both are height errors, so they are measured by metrology rather than found by defect scanners.
What is slurry residue?
Slurry residue is abrasive particles and polish byproduct still bonded to the wafer after the post-CMP clean. It blocks contact to the layer below, narrows spaces and seeds defects in the next deposition. Persistent residue is a verdict on the clean, and its signature points at the slurry batch or clean recipe behind it.
Is post-CMP cleaning the same as post-CMP inspection?
No. Post-CMP cleaning is the process step that removes slurry, particles and chemical residue from the polished surface, usually by brush cleaning with megasonic assist. Post-CMP inspection is the check that follows it, scanning the wafer to verify the clean worked and the polish left no scratches, delamination or corrosion behind.